Run some tests and report back if you have any issues. Note: Sync and properly eject the sd card as appropriate for your system. STEP 7: Copy the new *.bit.bin file to the boot partion of a Parallella SD card. $ source $XILINX_INSTALL_PATH/Xilinx/Vivado/2014.3.1/settings64.sh Run some “magical steps” using the Xilinx tools to convert the bit stream to a loadable bit stream. Make sure you have a dummy.elf in that directory. Create a file called ‘bit2bin.bif’ with the following contentī. There may be a better way of doing this…and if there isn’t there should be!! More than once I have forgotten to do this and gotten the error message: “Error: Timeout waiting for FPGA to config.Ī. This step maps the gate level netlist to the physical hardware inside the Zynq FPGA. This step converts the Verilog RTL to a gate level netlist and optimizes the logic.įind the right button to press in the GUI shown in the picture (or press F11). (parallella_7020_) STEP 3: Open the archived Vivado ProjectĬlick the ‘open project’ and point to the *.xpr file inside the folder you just unzipped. Note: Currently as of March 22 a headless 7020 project is available. Note#3: If you are running Ubuntu, edit the install script to use ‘/bin/bash’ instead of ‘/bin/sh’ (or change /bin/sh to point to bas instead of dash) STEP 2: Download and unzip the Parallella project Note#2: Due to permission issues, it’s easiest to install it in it in your home directory. Note#1: The download is large (>1GB), be patient. You will need to follow the Xilinx instructions to download and install the Vivado 2014.3 suite. For those of you who have never created HW before, this could be your first time:-) STEP 1: Download and Install the Vivado software The rest of this post is dedicated to getting you up and running with the elink and Vivado. If you feel like there are barriers in the way, tell me how we can remove those. Together we can move faster. A big part of this effort will be to more actively encourage contribution from outside Adapteva. Please consider this an open invitation to anyone with FPGA skills to contribute pull requests to the ‘parallella-hw’ repo. To anyone who has been stuck waiting for the new Vivado design, I am truly sorry for the delays! I am embarrassed that it has taken this long and I am doing everything I can to make sure this doesn’t happen again. More news on that development soon hopefully… The new elink design project has been tested extensively at Adapteva and has recently gone through beta testing by friends in Sweden working on an exciting “non-parallella” Zynq + Epiphany board. There is still optimization work to be done in terms of elink read/write performance, but I consider the new design to be a high quality starting point for future work. Last summer we started migrating the elink from Xilinx ISE to the new Vivado tools while also doing a complete overhaul of the design to improve performance, power, and maintainability.
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